|Opcode/Instruction||Op/En||64/32-bit Mode||CPUID Feature Flag||Description|
0F 6F /r
MOVQ mm, mm/m64
|RM||V/V||MMX||Move quadword from mm/m64 to mm.|
0F 7F /r
MOVQ mm/m64, mm
|MR||V/V||MMX||Move quadword from mm to mm/m64.|
F3 0F 7E /r
MOVQ xmm1, xmm2/m64
|RM||V/V||SSE2||Move quadword from xmm2/mem64 to xmm1.|
VEX.128.F3.0F.WIG 7E /r
VMOVQ xmm1, xmm2
|RM||V/V||AVX||Move quadword from xmm2 to xmm1.|
VEX.128.F3.0F.WIG 7E /r
VMOVQ xmm1, m64
|RM||V/V||AVX||Load quadword from m64 to xmm1.|
66 0F D6 /r
MOVQ xmm2/m64, xmm1
|MR||V/V||SSE2||Move quadword from xmm1 to xmm2/mem64.|
VEX.128.66.0F.WIG D6 /r
VMOVQ xmm1/m64, xmm2
|MR||V/V||AVX||Move quadword from xmm2 register to xmm1/m64.|
|Op/En||Operand 1||Operand 2||Operand 3||Operand 4|
|RM||ModRM:reg (w)||ModRM:r/m (r)||NA||NA|
|MR||ModRM:r/m (w)||ModRM:reg (r)||NA||NA|
Copies a quadword from the source operand (second operand) to the destination operand (first operand). The source and destination operands can be MMX technology registers, XMM registers, or 64-bit memory locations. This instruction can be used to move a quadword between two MMX technology registers or between an MMX tech-nology register and a 64-bit memory location, or to move data between two XMM registers or between an XMM register and a 64-bit memory location. The instruction cannot be used to transfer data between memory locations.
When the source operand is an XMM register, the low quadword is moved; when the destination operand is an XMM register, the quadword is stored to the low quadword of the register, and the high quadword is cleared to all 0s.
In 64-bit mode, use of the REX prefix in the form of REX.R permits this instruction to access additional registers (XMM8-XMM15).
Note: In VEX.128.66.0F D6 instruction version, VEX.vvvv and VEX.L=1 are reserved and the former must be 1111b otherwise instructions will #UD.
Note: In VEX.128.F3.0F 7E version, VEX.vvvv and VEX.L=1 are reserved and the former must be 1111b, otherwise instructions will #UD.
MOVQ instruction when operating on MMX technology registers and memory locations: DEST ← SRC; MOVQ instruction when source and destination operands are XMM registers: DEST[63:0] ← SRC[63:0]; DEST[127:64] ← 0000000000000000H; MOVQ instruction when source operand is XMM register and destination operand is memory location: DEST ← SRC[63:0]; MOVQ instruction when source operand is memory location and destination operand is XMM register: DEST[63:0] ← SRC; DEST[127:64] ← 0000000000000000H; VMOVQ (VEX.NDS.128.F3.0F 7E) with XMM register source and destination: DEST[63:0] ← SRC[63:0] DEST[VLMAX-1:64] ← 0 VMOVQ (VEX.128.66.0F D6) with XMM register source and destination: DEST[63:0] ← SRC[63:0] DEST[VLMAX-1:64] ← 0 VMOVQ (7E) with memory source: DEST[63:0] ← SRC[63:0] DEST[VLMAX-1:64] ← 0 VMOVQ (D6) with memory dest: DEST[63:0] ← SRC2[63:0]
m128i _mm_mov_epi64(__m128i a)
See Table 22-8, “Exception Conditions for Legacy SIMD/MMX Instructions without FP Exception,” in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B.