| Opcode/Instruction | Op / En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
|---|---|---|---|---|
| F3 0F 2C /r CVTTSS2SI r32, xmm1/m32 | A | V/V | SSE | Convert one single precision floating-point value from xmm1/m32 to one signed doubleword integer in r32 using truncation. |
| F3 REX.W 0F 2C /r CVTTSS2SI r64, xmm1/m32 | A | V/N.E. | SSE | Convert one single precision floating-point value from xmm1/m32 to one signed quadword integer in r64 using truncation. |
| VEX.LIG.F3.0F.W0 2C /r 1 VCVTTSS2SI r32, xmm1/m32 | A | V/V | AVX | Convert one single precision floating-point value from xmm1/m32 to one signed doubleword integer in r32 using truncation. |
| VEX.LIG.F3.0F.W1 2C /r 1 VCVTTSS2SI r64, xmm1/m32 | A | V/N.E.2 | AVX | Convert one single precision floating-point value from xmm1/m32 to one signed quadword integer in r64 using truncation. |
| EVEX.LLIG.F3.0F.W0 2C /r VCVTTSS2SI r32, xmm1/m32{sae} | B | V/V | AVX512F | Convert one single precision floating-point value from xmm1/m32 to one signed doubleword integer in r32 using truncation. |
| EVEX.LLIG.F3.0F.W1 2C /r VCVTTSS2SI r64, xmm1/m32{sae} | B | V/N.E.2 | AVX512F | Convert one single precision floating-point value from xmm1/m32 to one signed quadword integer in r64 using truncation. |
1. Software should ensure VCVTTSS2SI is encoded with VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may encounter unpredictable behavior across different processor generations.
2. For this specific instruction, VEX.W/EVEX.W in non-64 bit is ignored; the instructions behaves as if the W0 version is used.
| Op/En | Tuple Type | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|---|
| A | N/A | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A |
| B | Tuple1 Fixed | ModRM:reg (w) | ModRM:r/m (r) | N/A | N/A |
Converts a single precision floating-point value in the source operand (the second operand) to a signed doubleword integer (or signed quadword integer if operand size is 64 bits) in the destination operand (the first operand). The source operand can be an XMM register or a 32-bit memory location. The destination operand is a general purpose register. When the source operand is an XMM register, the single precision floating-point value is contained in the low doubleword of the register.
When a conversion is inexact, a truncated (round toward zero) result is returned. If a converted result is larger than the maximum signed doubleword integer, the floating-point invalid exception is raised. If this exception is masked, the indefinite integer value (80000000H or 80000000_00000000H if operand size is 64 bits) is returned.
Legacy SSE instructions: In 64-bit mode, Use of the REX.W prefix promotes the instruction to 64-bit operation. See the summary chart at the beginning of this section for encoding data and limits.
VEX.W1 and EVEX.W1 versions: promotes the instruction to produce 64-bit data in 64-bit mode.
Note: VEX.vvvv and EVEX.vvvv are reserved and must be 1111b, otherwise instructions will #UD.
Software should ensure VCVTTSS2SI is encoded with VEX.L=0. Encoding VCVTTSS2SI with VEX.L=1 may encounter unpredictable behavior across different processor generations.
IF 64-Bit Mode and OperandSize = 64
THEN
DEST[63:0] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
ELSE
DEST[31:0] := Convert_Single_Precision_Floating_Point_To_Integer_Truncate(SRC[31:0]);
FI;
VCVTTSS2SI int _mm_cvttss_i32( __m128 a);
VCVTTSS2SI int _mm_cvtt_roundss_i32( __m128 a, int sae);
VCVTTSS2SI __int64 _mm_cvttss_i64( __m128 a);
VCVTTSS2SI __int64 _mm_cvtt_roundss_i64( __m128 a, int sae);
CVTTSS2SI int _mm_cvttss_si32( __m128 a);
CVTTSS2SI __int64 _mm_cvttss_si64( __m128 a);
Invalid, Precision.
See Table 2-20, “Type 3 Class Exception Conditions,” additionally:
| #UD | If VEX.vvvv != 1111B. |
EVEX-encoded instructions, see Table 2-48, “Type E3NF Class Exception Conditions.”