Opcode/Instruction | Op/En | 64/32 bit Mode Support | CPUID Feature Flag | Description |
---|---|---|---|---|
EVEX.512.66.0F38.W0 C8 /r VEXP2PS zmm1 {k1}{z}, zmm2/m512/m32bcst {sae} | A | V/V | AVX512ER | Computes approximations to the exponential 2^x (with less than 2^-23 of maximum relative error) of the packed single-precision floating-point values from zmm2/m512/m32bcst and stores the floating-point result in zmm1with writemask k1. |
Op/En Tuple Type Operand 1 Operand 2 Operand 3 Operand 4 | |||||
---|---|---|---|---|---|
A Full ModRM:reg (r, w) ModRM:r/m (r) N/A N/A |
Computes the approximate base-2 exponential evaluation of the single-precision floating-point values in the source operand (the second operand) and store the results in the destination operand (the first operand) using the write-mask k1. The approximate base-2 exponential is evaluated with less than 2^-23 of relative error.
Denormal input values are treated as zeros and do not signal #DE, irrespective of MXCSR.DAZ. Denormal results are flushed to zeros and do not signal #UE, irrespective of MXCSR.FTZ.
The source operand is a ZMM register, a 512-bit memory location, or a 512-bit vector broadcasted from a 32-bit memory location. The destination operand is a ZMM register, conditionally updated using writemask k1.
EVEX.vvvv is reserved and must be 1111b otherwise instructions will #UD.
(KL, VL) = (16, 512) FOR j := 0 TO KL-1 i := j * 32 IF k1[j] OR *no writemask* THEN IF (EVEX.b = 1) AND (SRC *is memory*) THEN DEST[i+31:i] := EXP2_23_SP(SRC[31:0]) ELSE DEST[i+31:i] := EXP2_23_SP(SRC[i+31:i]) FI; ELSE IF *merging-masking* ; merging-masking THEN *DEST[i+31:i] remains unchanged* ELSE ; zeroing-masking DEST[i+31:i] := 0 FI; FI; ENDFOR;
Source Input | Result | Comments |
---|---|---|
NaN | QNaN(src) | If (SRC = SNaN) then #I |
+∞ | +∞ | |
+/-0 | 1.0f | Exact result |
-∞ | +0.0f | |
Integral value N | 2^ (N) | Exact result |
VEXP2PS __m512 _mm512_exp2a23_round_ps (__m512 a, int sae);
VEXP2PS __m512 _mm512_mask_exp2a23_round_ps (__m512 a, __mmask16 m, __m512 b, int sae);
VEXP2PS __m512 _mm512_maskz_exp2a23_round_ps (__mmask16 m, __m512 b, int sae);
Invalid (if SNaN input), Overflow.
See Table 2-46, “Type E2 Class Exception Conditions.”